This application claims the benefit, under 35 U.S.C. §119, of Korean Patent Application No. 10-2005-0015038, filed on Feb. 23, 2005, in the Korean Intellectual Property Office, which is incorporated herein in its entirety by reference.
1 . Field of the Invention
The present invention relates to a solid state image sensing device and, more particularly, to a CMOS image sensor (CIS) type image sensing device for averaging and sub-sampling analog image signals (as may be required for producing moving pictures) at a variable sub-sampling rate, and a method of driving the same.
2. Description of the Related Art
A typical solid state image sensing devices is either classified as a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) type device or a charge-coupled device (CCD). Recently, the manufacture of CIS type devices has surpassed that of the CCD type and are used in a variety of fields because the CIS type requires a lower operating voltage and a lower power consumption than that of the CCD type and it may fabricated using a standard CMOS technology and easily integrated with other circuits on the same chip.
CIS type solid state image sensing devices are now commonly mounted in cellular phones (camera phones) and addition to digital still cameras, to capture an image, convert the captured image into an electronic image signal and to transmits the electronic image signal as color image data to a digital signal processor (DSP) for further processing. The digital signal processor DSP processes color image data RGB output from the solid state image sensing device to drive a display device such as a liquid crystal display (LCD).
In a system employing the CIS type solid state image sensing device, a sub-sampling mode of the CIS device outputs an image signal having a reduced vertical resolution. The sub-sampling mode supports a higher frame rate and supports displaying a moving picture, a quick preview for confirming an image before capturing the whole image, and for automatic focusing systems.
FIG. 1 is a block diagram of a conventional complementary metal-oxide semiconductor (CMOS) image sensor (CIS) type solid state image sensing device 100. Referring to FIG. 1, the conventional CIS device 100 includes an active pixel sensor (APS) array 110, a row driver 120 and an analog-to-digital conversion (ADC) unit 130. The row driver 120 receives a control signal from a row decoder (not shown) and the analog-to-digital conversion (ADC) unit 130 receives a control signal from a column decoder (not shown). The CIS device 100 further includes a controller (not shown) that generates timing control signals and addressing signals for outputting a selected and sensed image signal of each pixel.
FIG. 2 is a diagram illustrating the color pixel arrangement of the APS array 110 shown in FIG. 1.
In the CIS device 100, in general, a color filter is arranged over each of the pixels in the APS array 110 such that only (filtered) light of a specific color is received by each pixel. To construct color image signals, at least three colors of filters are arranged on the APS array 110. A general color filter array has Bayer pattern, as shown in FIG. 2, in which, for each set of four color pixels representing one image pixel, two red and green color pixels are arranged in one row and two green and blue color pixels are arranged in another row. Thus in the Bayer Pattern, as shown in FIG. 2, the green color pixels (the most closely related to a luminance signal) are arranged in all rows while the red and blue color pixels are arranged in alternate rows, to improve luminance resolution. A CIS having more than one million color pixels is typically used in a digital still camera in order to provide a suitable image resolution.
The operation of the APS array 110 will now be in detail described with reference to FIGS. 1 and 2.
In the CIS type (solid state image sensing) device 100, each pixel in the APS array 110 senses light using a photodiode (not shown) and converts the sensed light into electric signals to generate image signals. The image signals are output from the APS array 110 as analog signals corresponding to the colors red (R), green (G) and blue (B).
The APS array 110 is constructed in such a manner that the color pixels are arranged in a two-dimensional matrix. A color filter disposed on the APS array 110 typically has the Bayer pattern in which a first two-color sequences of first and second color pixels (e.g., G and B) are arranged in one row and a second two-color pattern of first and third pixels G and R are arranged in another (adjacent) row. However, the color filter is not limited to the Bayer pattern because the pixel array pattern can be constructed in various ways.
A mechanical shutter is opened to allow light to accumulate charges in photodiodes included in the APS array 110 for a predetermined period of time. While the charges are being accumulated in the photodiodes, the APS array 110 generates and outputs the reset signals VRES in response to the reset control signal RG. The final quantity of charges accumulated in each of the photodiodes (when the mechanical shutter closes) is detected in a sequence according to the transfer control signal TG generated by the row driver 120. Assuming that the color filter has the Bayer pattern, the APS array 110 outputs from all columns the first color signals G and the second color signals B from one row of photodiodes, and next outputs from all columns the third color signals R and the first color signals G from the next row, etc. in an image mode. Whenever the photodiode senses light for a predetermined period, the APS array 110 outputs the reset signal to the analog-to-digital conversion unit 130 before the photodiode outputs the sensed image signal to the analog-to-digital conversion unit 130. The analog-to-digital conversion unit 110 receives the reset signal and is reset by it, and then converts the image signal received from the photodiode into a digital signal. The digital signal is output to a digital signal processor and (may be interpolated).
When the CIS device captures a still image, image signals of all the color pixels, sensed by photodiodes of the APS array 110 are output. However, in the sub-sampling mode including for moving picture display, preview and automatic focus, horizontal and vertical resolutions are reduced and image signals are output.
In the conventional CIS device 100 shown in FIG. 1, the analog-to-digital conversion (ADC) unit 130 converts an image signals sensed by the photodiodes into a digital signal. The resolution may be reduced (in the sub-sampling mode) using a correlated double sampling (CDS) method, which is disclosed in U.S. Pat. No. 5,982,318 and U.S. Pat. No. 6,067,113.
Correlated double sampling (CDS) analog-to-digital conversion samples each pixel twice, once for its reset (reference) level and once for the actual image signal. The reference level is subtracted from the image signal, and the difference is amplified and output. Double sampling of the signal eliminates correlated noise that affects both the reference level and the image signal of each pixel. Correlated double sampling (CDS) analog-to-digital conversion includes two steps: first, of receiving a reset signal from the APS array 110 and second, en receiving an image signal sensed by the photodiode, to convert the image signal into a digital signal. The digital signal processor generates a driving signal suitable for the resolution of a display device such as LCD to display the image on the display device.
In the case of a CIS device having an APS array with super extended graphic adapter (SXGA) resolution, for example, the CIS device outputs SXGA-grade image signals when it photographs a still image. However, the CIS device outputs video graphic adapter (VGA)-grade image signals in sub-sampling mode operations. For reference, the number of pixels of SXGA resolution is 1280×1024 and the number of pixels of VGA resolution is 640×480.
Even a CIS device having an APS array with ultra extended graphics adapter (UXGA) resolution may output image signals with less than VGA-grade resolution in the sub-sampling mode to reduce the quantity of processed data. For reference, the number of pixels of UXGA resolution is 1600×1200.
In the sub-sampling mode of the conventional CIS device 100, only image signals of predetermined specific rows and columns are output to the analog-to-digital conversion unit 130, to reduce vertical resolution.
To decrease the SXGA resolution to the VGA resolution, for instance, only a single data corresponding to one pixel at the intersection of one row and column selected from a set of corresponding two rows and two columns, and other data items are removed such that resolution is reduced by half.
When only data corresponding to one row and column is selected from data items corresponding to many (e.g., two or more) rows and columns, the resolution can be further reduced, and thus the quantity of processed data can be further decreased.
However, there exits image data that is not used but is discarded in the sub-sampling mode of the conventional CIS device 100. This causes aliasing noise such that oblique lines on a display are not smoothly connected but may be shown as a zigzag.
To remove the aliasing noise, a method of averaging all image signals in a predetermined range and outputting the averaged image signal has been proposed. The known image signals averaging methods includes: a method of analog-averaging image signals in a predetermined range before image signals sensed by pixels are output to the analog-to-digital conversion ADC unit 130; a method of digital-averaging corresponding digital signals output from the analog-to-digital conversion unit 130.
FIG. 3 is a block diagram of a conventional CIS type solid state image sensing device 300 for digital-averaging of digital signals. Referring to FIG. 3, the operations of an APS array 310 and a row driver 320 are the same as the operations of the APS array 110 and the row driver 120 shown in FIG. 1 so that further explanations thereof are left out.
An analog-to-digital conversion (ADC) unit 330 of the conventional CIS device 300 includes a correlated double sampling (CDS) unit 331 (including a plurality of CDS circuits) and a digital averaging & signal output unit 333. The digital averaging & signal output unit 333 digitally -averages output (digital) signals of the CDS unit 331 and outputs the averaged digital signals to a subsequent digital signal processor (not shown).
FIG. 4 is a block diagram of the correlated double sampling CDS unit 331 shown in FIG. 3. Referring to FIG. 4, each of the plurality of CDS circuits in the CDS unit 331 is connected to one column of the APS array 310 (FIG. 3) and performs an analog-to-digital conversion (a column ADC method) of received analog image signals in the attached column. Each of the plurality of CDS circuits performs a CDS operation with a reset signal (e.g., VRES1, VRES2, . . . and an image signal (SVIG1, VSIG2, . . . ) sensed by pixels, and performs the analog-to-digital conversion using a ramp signal VRAMP generated in a ramp signal generator (not shown). Each of the plurality of CDS circuits outputs a digital signal VCD1.
FIG. 5 is a circuit diagram of one of the correlated double sampling (CDS) circuits 500 (e.g., one of 500-1, or 500-2, etc.) shown in FIG. 4. Referring to FIG. 5, the CDS circuit 500 sequentially receives a reset signal VRES and an image signal VSIG, then compares the resulting voltage signal (corresponding to the difference between the reset signal VRES and the image signal VSIG) with a predetermined reference voltage VREF, and outputs a signal VCD having a modulated pulse width in response to the comparison result.
Each of correlated double sampling CDS circuits 500 (e.g., 500-1, 500-2, 5003, etc.) includes first, second, third and fourth switches S1, S2, S3, and S4, first, second and third capacitors C1, C0, and C2, and first and second amplifiers AMP1 and AMP2. The operation of the correlated double sampling CDS circuit 500 will now be described with reference to FIG. 5.
If the CDS circuit 500 sequentially receives the reset signal VRES and the image signal VSIG and the first through fourth switches S1˜S4 are turned ON (i.e., closed) and OFF (i.e., open) at appropriate times, a (voltage) signal VIN corresponding to a difference between the reset signal VRES and the image signal VSIG is applied to the negative input terminal of the first amplifier AMP1. Then, switches S1, S3, and S4 are turned OFF (i.e., opened).
At this time, if a ramp signal VRAMP rises, the input signal VIN increases with the ramp signal VRAMP. The first amplifier AMP1 compares the input signal VIN with the predetermined reference voltage VREF and outputs an output signal VOUT having a pulse width in response to the comparison result.
The second amplifier AMP2 buffers the output signal VOUT1 from the third capacitor C2 and outputs the pulse width modulated signal VCD.
Output signals of each CDS circuit 500 (e.g., 500-1, 500-2, 5003, etc.) are digitally averaged and the digitally averaged digital image signal is transmitted to the subsequent digital signal processor (not shown).
However, digital averaging requires a large-capacity memory so that the chip area and power consumption are increased. Accordingly, the conventional CIS solid state image sensing device with conventional CDS operation is difficult to apply to small-size mobile apparatuses.